It is well known to provide a test access port for testing an integrated circuit. A typical circuit includes a test access port (TAP) for example one complying with the IEEE 1149.1 Standard. As the TAP and the module likely use different clocks, an interface is required. The TAP signals shown correspond to the ones used by the IEEE 1149.1 standard. The TAP allows initializing and collecting of the results of the test controller during system maintenance. Signals can be exchanged directly between the test controller and the rest of the module to be tested because they are part of the same clock domain. High-speed testing of the module is therefore possible. However, a special interface between the TAP and the test controller must be designed to enable the exchange of signals.
In the prior art, there are at least 2 ways suggested to make this data transfer possible. The first one is to intercept the clock of the module under test with a multiplexer and substitute it with the TAP clock during the transfer of the serial data. Once the data has been loaded in the registers, they are configured in a holding mode and the module clock is switched back to the original clock frequency. The holding mode is necessary to make sure that the registers keep the value they were programmed to while the clocks are switched since unintended clock pulses are likely to occur at that time because of the unknown phase relationship between the clocks in most systems. This method is attractive due to its relatively low cost as it requires only one additional multiplexer per flip-flop in the test controller to implement the holding mode. However, it is necessary to interrupt the normal system function while the data transfer takes place. This is not always desirable since some of the test functions require the system to be running normally. Another disadvantage is that in many high-speed applications, a phase-lock loop (PLL) is used to compensate phase differences between the input and output of the circuit. The PLL may take a long time to resynchronize after it has been disabled for the duration of the serial data transfer. Finally, the glitches generated on the clock lines may cause the simulation of the circuit to fail due to the pessimistic assumptions made in the models and the simulators themselves.
A second method is to use "shadow" registers, that is to duplicate all flip-flops of the test controller and connect their clock to the clock of the TAP. To initialize the test controller, data is first shifted in the shadow register. When all the data has been shifted in, the register is put in a holding mode similar to the one described above or the TAP clock is stopped. A signal from the TAP indicating that the data is ready to be transferred is sent to the test controller which resynchronizes it by sampling it with 2 consecutive flip-flops. The synchronized signal is then distributed to all flip-flops of the test controller that can then safely load the data in the shadow register. A similar process is used to send data back to the TAP. The advantage of this method compared to the first one is that the system clock does not need to be interrupted during the initialization and reading of the test registers. The main drawback of this method is its relatively high cost because of the duplication of all the registers of the test controller.